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lib/Conversion/ImportVerilog
test/Conversion/ImportVerilog Expand file tree Collapse file tree 2 files changed +15
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lines changed Original file line number Diff line number Diff line change @@ -1888,6 +1888,9 @@ LogicalResult Context::convertNOutputPrimitive(
18881888 llvm::StringSwitch<std::function<Value ()>>(prim.primitiveType .name )
18891889 .Case (" not" ,
18901890 ([&] { return moore::NotOp::create (builder, loc, inputVal); }))
1891+ .Case (" buf" , ([&] {
1892+ return moore::BoolCastOp::create (builder, loc, inputVal);
1893+ }))
18911894 .Default ([&] {
18921895 mlir::emitError (loc)
18931896 << " unsupported primitive `" << primName << " `" ;
Original file line number Diff line number Diff line change @@ -158,3 +158,15 @@ module multi_not_prim;
158158 logic A , Q0 , Q1 ;
159159 not n (Q0 , Q1 , A );
160160endmodule
161+
162+ // CHECK-LABEL: moore.module @buf_prim()
163+ // CHECK: [[A:%.+]] = moore.variable : <l1>
164+ // CHECK: [[Q:%.+]] = moore.variable : <l1>
165+ // CHECK: [[RD_A:%.+]] = moore.read [[A]] : <l1>
166+ // CHECK: [[NOT:%.+]] = moore.bool_cast [[RD_A]] : l1
167+ // CHECK: moore.assign [[Q]], [[NOT]] : l1
168+
169+ module buf_prim ;
170+ logic A , Q ;
171+ buf n (Q , A );
172+ endmodule
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